Pushing the Boundaries of SiC Wafer Processing: Achieving Ultra-Low Geometry in Large-Diameter Wafers
Pushing the Boundaries of SiC Wafer Processing: Achieving Ultra-Low Geometry in Large-Diameter Wafers
As the silicon carbide (SiC) industry moves toward larger and thinner wafers, one factor increasingly defines success: geometry. Beyond crystal growth and defect density, wafer shape precision has become the ultimate performance gatekeeper. A few microns of deviation can determine whether a line runs efficiently or bleeds yield and cost. At ICSCRM 2025 in Busan, Pureon’s Chief Innovation Officer, Dr. William Gemmill, presented the company’s latest advances in achieving ultra-low wafer geometries. The talk introduced an integrated approach – from rapid thinning to final CMP – that enables sub-micron geometry control at production scale. Through innovations in consumables, process design, and CMP template technology, Pureon showed how research-level precision can now be achieved in high-volume manufacturing.
The 8-inch Breakthrough and the 12-inch Horizon
The industry’s steady shift from 6-inch (150 mm) to 8-inch (200 mm) SiC wafers is no longer an experiment; it’s a mainstream production reality. Multiple device manufacturers are now qualifying 8-inch wafers for volume lines, motivated by the same forces that once drove silicon’s scaling trajectory: reduced cost per die, higher throughput, and supply consolidation.
But while the economics favor larger diameters, the physics resist them. With 8-inch wafers already pushing the mechanical and thermal limits of SiC, the introduction of 12-inch substrates magnifies every geometric challenge tenfold. Bow, warp, and TTV no longer stay in the background – they define process viability.
This evolution elevates ultra-low wafer geometry from a technical differentiator to an industrial survival factor. Scaling to 12-inch wafers without mastering geometry control would simply amplify cost and yield pain points instead of solving them. The work presented by Pureon shows how integrated process solutions bridge that gap – turning scaling ambition into manufacturable reality.
Why wafer geometry matters
In SiC wafer production, geometry precision directly determines downstream performance. Parameters such as Total Thickness Variation (TTV), Local Thickness Variation (LTV), and Site Flatness (SFQR) govern how uniformly epitaxial layers grow and how accurately lithography aligns. Even minimal distortions can propagate through the process chain, lowering yields and pushing up costs.
With the industry transitioning from 150 mm to 200 mm substrates – and preparing for 300 mm pilot lines – control windows are narrowing further. Wafers must be flatter, thinner, and more stable than ever before. Ultra-low geometry variation has therefore become essential not only for technical performance but also for the economics of SiC manufacturing.
Total Process Solutions
Building on more than two decades of expertise in SiC wafering, Pureon has developed a comprehensive strategy that considers every stage of the manufacturing process – from slicing to final polishing. This approach rests on three principles:
- Scalability and cost of ownership – Ensuring industrial throughput without compromising precision.
- Process stability and yields – Engineering consumables for consistent results over multiple runs and tool platforms.
- Collaboration and supply security – Partnering with leading equipment manufacturers and operating production sites in Asia, the US, and Europe to safeguard supply chains.
This framework positions Pureon as a roadmap solution provider for the SiC ecosystem, helping customers scale confidently while maintaining quality and repeatability.
Rapid Thinning: The bridge between slicing and CMP
At the heart of Pureon’s strategy lies its Rapid Thinning Process, designed to connect as-sawn wafers to final CMP with minimal geometry drift. Using a precision double-sided polishing platform, together with IRINO-ProSiC composite lapping pads and PURE-DS-RT diamond suspensions, Pureon achieved exceptional control under real manufacturing conditions.
Test setup:
- Tool: AC1200
- Pad/Slurry: IRINO-ProSiC & PURE-DS-RT
- Flow rate: 40 mL/min
- Workpieces: 12 × 150 mm SiC wafers (as-sawn)
- Runs: Run 1 (5 min), Runs 2–6 (20 min each)
- No pad dressing between runs
The result:
Even after extended operation, TTV values remained below 1 µm, with virtually no edge-roll and only a slight wedge (< 1 µm) observed. Each process step removed roughly 20 µm per wafer while maintaining geometry stability throughout multiple runs – without intermediate pad conditioning and low pad wear. This combination of throughput, precision, and consistency represents a decisive advance for volume wafering operations.
Consumable innovations that make it possible
Reaching sub-micron geometry accuracy depends on consumables engineered for stability and control. Pureon’s recent developments focus on two critical components:
- Diamond suspensions (PURE-DS–RT): Formulated for high material-removal rates with minimal micro-chipping, ensuring uniform thinning and smooth surfaces ready for CMP.
- Grinding pads (IRINO-ProSiC): Designed for long-run stability, delivering steady removal rates and preserving wafer geometry without frequent pad dressing.
These materials eliminate the long-standing compromise between removal rate and precision, enabling faster, more consistent processing.
Advanced template design: correcting geometry at the final stage
Chemical-mechanical polishing (CMP) is essential for achieving device-grade surfaces but can introduce shape distortion if pressure and compliance are not properly managed. Pureon’s research in composite template design addresses this directly. The latest templates integrate:
- Rigid substrates and backers for mechanical support
- Compressible films to balance downforce
- Optimized topper layers for even contact across the wafer
Applied to single-side CMP (~ 0.5 – 0.75 µm removal on Si Face), these templates showed notable post-CMP geometry improvements, effectively compensating minor deviations accumulated earlier in the process.
For 8-inch and 12-inch wafers, this adaptive compliance becomes critical.
Larger diameters amplify any asymmetry in tool pressure and carrier design. By fine-tuning template stiffness gradients and using calibrated thermal expansion layers, Pureon’s advanced templates ensure geometry correction remains stable across size transitions.
From data to impact
The results from these integrated strategies are clear:
- Consistent TTV performance across extended production runs
- No geometry drift despite multiple passes and no pad dressing
- Predictable material-removal rates and surface finish at high throughput
- Sub-micron correction capability during CMP
For manufacturers, these achievements translate directly into higher yields, less rework, and lower cost of ownership – the essential ingredients for scaling SiC wafer production sustainably.
Collaborative innovation and global readiness
The transition to 8-inch mainstream production and early 12-inch R&D requires more than equipment—it demands ecosystem alignment. By working closely with tool makers, wafer suppliers, and device manufacturers, Pureon supports customers through every scaling phase.
Production facilities in Asia, the US, and Europe provide regional availability, ensuring that next-generation SiC fabs can adopt advanced geometry processes without supply risk. This collaboration allows Pureon to validate new process flows directly on pilot 12-inch tools, accelerating the time from concept to production readiness.
Geometry as the new frontier
The next leap in SiC wafer manufacturing will not come from speed alone but from control – control over geometry, uniformity, and repeatability. The move to 8-inch mainstream and the 12-inch frontier only sharpens this truth: scaling succeeds when precision scales with it.
The work presented by Pureon at ICSCRM 2025 made this clear: ultra-low wafer geometries are the foundation for scalable, high-yield, and cost-efficient SiC production. Through innovations in rapid thinning, suspension chemistry, and advanced template design, Pureon is helping the industry move from incremental optimization toward a new era of precision manufacturing.
References
Pureon AG. (2025, August 8). Strategies for Ultra-Low Wafer Geometries in SiC Wafer Processing: ICSCRM 2025 – Industrial Session Presentation (V1). Internal presentation, Busan, South Korea.
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